1. Field of the Invention
The present invention relates to sensing circuits for semiconductor memories, and more particularly to a sensing circuit including pulsed sensing clocks for limiting bitline voltage swings.
2. Background Art
No pertinent prior art is known. Background art to alternative technologies are as follows.
U.S. Pat. No. 4,816,706 issued Mar. 28, 1989 to Dhong et al entitled "SENSE AMPLIFIER WITH IMPROVED BITLINE PRECHARGING FOR DYNAMIC RANDOM ACCESS MEMORY" discloses a novel sense amplifier and decoupling device structure for integrated circuit memories wherein an embodiment of a cross-coupled sense amplifier includes two PMOS devices, the gates of which devices are grounded and clamp the downward voltage swing of the memory bitlines to the absolute value of the threshold voltage (VTP) of the grounded-gate PMOS devices in the sense amplifier. This limited voltage swing does not affect charge storage of storage capacitors because the absolute value of the threshold voltage (VT) of the cell transfer gate device is larger. Precharging the bitlines is achieved by equalizing the two bitlines, each charge to VDD and .vertline.VTP.vertline., respectively. One node of the sense amplifier retains a full VDD swing and is conveniently connected to the DATA bus. The sense amplifier bitline swing is limited to a swing of VDD-.vertline.VTP.vertline. and saves power without adversely affecting charge storage and the precharging level.
The IBM Technical Disclosure Bulletin, Vol. 32, No. 10B, March 1990 on pages 427-429 includes a publication by K. S. Gray entitled "REDUCED VOLTAGE BITLINE RESTORE CIRCUIT" discloses a voltage reducing circuit for a semiconductor memory shown whereon the bitline pull-up voltage level may be less than the supply voltage VDD.